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Arm/FPGA“Aa~AIr
2018-04-18

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첻zAƼ˞иIṩMQԼaھҲ_ʼ𲽌˹ҪC_OĠBɜy/\ࡢԭ/ԴʹàraƷƷ̵𲽌˹\(Arm)Ĺؔ(IP)cSoCِ`˼(Xilinx)ĬFɾT(FPGA)gtAƄaAIăɴ

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      IAIgҲ׷ߵķԡDeepmindµGo()õQAlphaԓҲձҽB@o˹ܷlչһҪ̱

      ڿݻcNIr˹ܳǰĿĿƼh}ӑՓwӑՓڸиI˹FaIܻ߀кܶ}Ҫ˷

 

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˹ҪKPIҪչF˹Ϸăcf׃ɿM˵UɢAIһҪĿ

 

^ҪFĴ󃞻Ҫ߀IAI̶ԼѼ|ÉġI߱ҪAI_JR֪AIm̎}кΣAIՓģ͵ӖɹģͱӖ|ҲҪ|}ӖģAIՓYFrF

MĻҲ{AI֮ǰaQ߶^AIKQmȻ߀ֻ{^ĸX^W˸C֮gهPϵҪһrgȻAIҲҪmMAyĿɿȸʴ_

ͬ̎LArmܘmՓ\

Mһ˹ܿԷֳģӖ(Training)cՓ(Inference)ɂaFfDzӖõģиNՓֱ߅MģӖģӖҪ\Чܸ^mĻƶMС

ҲՓ\Чܵ^SFɵ̎Q܄x86 CPUGPUcArmܘSoC̎P\eֻڳɱǷMFOҎơ

ͼgǶȶGPUĿǰmMģӖ̎ܘģՓծȻҲbbGPUijɱĸS֮ɢᆖ}s߅cFO䑪x86 CPUҲк\ЧܣܘĿMN\/AIrЧʲGPU

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þָ(RISC)Arm̎tGPUx86 CPU֮gϽArm̎һָ(Single Instruction, Multiple Data, SIMD)ЧܲAI\r֡mȻĿǰҪArm̎ģӖ߀DzܸGPUȣՓՕrsǹġɱЧƽķ

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oץ˹ϷĴҪأA_ʼArmܘSoCِ`˼FPGAģKӲAԼҵau˹

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A̎hǵ͵aBһMaƷҎһaкܴIJͬaĹҲs@ҲA˹rϣܽQʹc֮һ

|ܱʾڼgϵĿǰ߀oFȫϵyxԭʼKOĿ@AδŬķ

wfδAϣFĿһaOFϣеęC_Oֹ֧I4.0FɼcܛĽҪӵϵy(MES)aƷڹ(PLM)ϵyCҕXcWMһUƷhС

һc|ܲMFЙC_ͨҪrͣeҪԭSṩֻ֧Լָĵr^ijЩr£FЙC_͸^AԼ_lɼģK@

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FPGAģKFCҕX

CҕXFPGAģKչֵ_ҲAFPGAlչFĿ֮һ͸^FPGAģKAQЩӰRhҪӲҕXzyϵy\Ч 

ָCPUGPUʹõӲоƬAIϵyЧՓҲһlе·^ĿǰAI߀ڿMASICܿ׷ϼglչ_FPGAtЧcԵ\ԪYԿƻMض㷨ٵԣ㷨Ҫ޸Ļµr_һwоƬֻҪ޸a

FAFPGA팍FAI㷨ٵ뷽֮һAҲFPGA_lFδ^mͶY@g

 

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